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Implementation Technical Lead, SoC DFE ASIC Top

Nokia Solutions and Networks Oy, Oulu Oulu

Implementation Technical Lead, SoC DFE ASIC Top

About Nokia

Nokia is a global leader in the technologies that connect people and things. With state-of-the-art software, hardware and services for any type of network, Nokia is uniquely positioned to help communication service providers, governments, and large enterprises deliver on the promise of 5G, the Cloud and the Internet of Things. Serving customers in over 100 countries, our research scientists and engineers continue to invent and accelerate new technologies that will increasingly transform the way people and things communicate and connect.

We are looking for a SoC Implementation Technical Lead (Synthesis & STA) Engineer to System-on-Chip DU organization


We are looking for an engineer interested in SoC Hard Macro & top-level implementation activities. An engineer who is willing to do and lead SoC implementation activities and capable to use the needed tools. A 6+ years of SOC/FPGA implementation experience is expected. In addition, any experience with SoC/FPGA/IP development is considered as an advantage.

You have a hungry mind to learn more and you are excited doing a variety of different kinds of tasks as part of your job. You are always ready to share your knowledge and skills among the people you work with. You are a team worker but also efficient on independent tasks, and your English language skills allow you communicate efficiently in our multicultural environment.

Main Responsibility Area

Basic requirements for implementation technical lead are very good understanding and practical experience of synthesis, STA, timing closure and formal verification. The precise job description of the main tasks can be tailored based on your interest and experience.

Job Description:

Participate in outlining and leading System-on-Chip top-level activities

Work with various design groups across different disciplines (RTL design, verification, DFT & layout) to meet timing closure, area, power, and performance requirements.
Perform logic synthesis, logic equivalence checking, static timing analysis, power estimation and hand-off checks using best-in-class methodologies
Analyze log and report files to ensure the tools are getting the required results.
Develop the scripts to get the required results within the scheduled milestones
Advising RTL designers and junior implementation designers related to constraints, timing closure & vendor requirements

Additional Requirements:

Bachelor's or Master's Degree in Engineering or equivalent
6+ years working experience in FPGA/ASIC/SoC development
Familiar with digital design and UNIX/LINUX environment
Knowledge of ARM standards, processors and interconnects
Good understanding of RTL design and RTL requirements for synthesis
Good experience of scripting languages like TCL, Python, Perl
Good knowledge of SoC (ASIC/FPGA) implementation tools
Understanding of Cellular networks and 2G, 3G, LTE and 5G technology
Fluent spoken and written English

Beneficial skills:

Low power understanding
Experience of DFT, P&R or floor planning
Knowhow of packages, thermal, testing, product engineering
Työpaikan osoiteKaapelitie 4, 90620 OULU
Työkokemusyli 5 vuotta
Työ alkaaAccording to agreement
Työn kestoyli 12 kuukautta
Haku päättyy17.12.2021
Hakulomakkeen WWW-osoite
Ilmoitus jätetty17.09.2021

Lähde: Työ- ja elinkeinotoimisto

36 päivää sitten

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